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CHIP DESIGN FOR SUBMICRON VLSI CMOS LAYOUT AND SIMULATION

By: UYEMURA, J. PMaterial type: Text

TextLanguage: ENGLISH Publication details: NEW DELHI CENGAGE LEARNING 2009Edition: 1STDescription: NA NASubject(s): NA | NADDC classification: 621.384.6

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Item type	Current library	Home library	Call number	Status	Barcode
Books	School of Engineering and Technology PKD REFERENCE SECTION	School of Engineering and Technology PKD	621.384.6 (Browse shelf (Opens below))	Not For Loan	BT-22583
Books	School of Engineering and Technology PKD REFERENCE SECTION	School of Engineering and Technology PKD	621.384.6 (Browse shelf (Opens below))	Not For Loan	BT-22584
Books	School of Engineering and Technology PKD REFERENCE SECTION	School of Engineering and Technology PKD	621.384.6 (Browse shelf (Opens below))	Not For Loan	BT-22585
Books	School of Engineering and Technology PKD REFERENCE SECTION	School of Engineering and Technology PKD	621.384.6 (Browse shelf (Opens below))	Not For Loan	BT-22586
Books	School of Engineering and Technology PKD REFERENCE SECTION	School of Engineering and Technology PKD	621.384.6 (Browse shelf (Opens below))	Not For Loan	BT-22587

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Previous	621.384.6 DIGITAL LOGIC DESIGN	621.384.6 CHIP DESIGN FOR SUBMICRON VLSI CMOS LAYOUT AND SIMULATION	621.384.6 CHIP DESIGN FOR SUBMICRON VLSI CMOS LAYOUT AND SIMULATION	621.384.6 CHIP DESIGN FOR SUBMICRON VLSI CMOS LAYOUT AND SIMULATION	621.384.6 CHIP DESIGN FOR SUBMICRON VLSI CMOS LAYOUT AND SIMULATION	621.384.6 CHIP DESIGN FOR SUBMICRON VLSI CMOS LAYOUT AND SIMULATION	621.384.6 A VHDL PRIMER	Next

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