CHIP DESIGN FOR SUBMICRON VLSI CMOS LAYOUT AND SIMULATION

By: UYEMURA, J. PMaterial type: TextTextLanguage: ENGLISH Publication details: NEW DELHI CENGAGE LEARNING 2009Edition: 1STDescription: NA NASubject(s): NA | NADDC classification: 621.384.6
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Books Books School of Engineering and Technology PKD
REFERENCE SECTION
School of Engineering and Technology PKD
621.384.6 (Browse shelf (Opens below)) Not For Loan BT-22583
Books Books School of Engineering and Technology PKD
REFERENCE SECTION
School of Engineering and Technology PKD
621.384.6 (Browse shelf (Opens below)) Not For Loan BT-22584
Books Books School of Engineering and Technology PKD
REFERENCE SECTION
School of Engineering and Technology PKD
621.384.6 (Browse shelf (Opens below)) Not For Loan BT-22585
Books Books School of Engineering and Technology PKD
REFERENCE SECTION
School of Engineering and Technology PKD
621.384.6 (Browse shelf (Opens below)) Not For Loan BT-22586
Books Books School of Engineering and Technology PKD
REFERENCE SECTION
School of Engineering and Technology PKD
621.384.6 (Browse shelf (Opens below)) Not For Loan BT-22587

CR-2261

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